A fundamental design challenge in creating a memory cell of an electrically erasable programmable read only memory (EEPROM) device is to use a controllable and reproducible electrical effect that has sufficient non-linearity so that the memory cell (1) can be written to (or erased) at one voltage in less than one millisecond (1 ms) and can be read at another voltage, and (2) the data within the memory cell must remain unchanged for more than ten (10) years.
Prior art stacked/split gate EEPROM technology requires (1) special multi-polysilicon materials, (2) different gate oxide thicknesses, and (3) modified doping profiles. These prior art requirements create process complexity and high cost when embedded into a complementary metal oxide semiconductor (CMOS) process.
It is well known that CMOS compatible non volatile memory (NVM) devices often experience additional charge leakage through backend dielectric layers. The charge leakage through backend dielectric layers is in addition to the charge leakage that NVM devices experience through the front end gate oxide layer in stacked gate NVM devices.
FIG. 1 illustrates a schematic cross sectional diagram of an exemplary prior art non volatile memory (NVM) cell 100. Memory cell 100 comprises a polysilicon gate 110 (designated “POLY GATE 110” in FIG. 1). Polysilicon gate 110 and other elements of the memory cell 100 are covered with backend dielectric 120. In this example backend dielectric 120 is made of tetraethyloxysilane (TEOS). Therefore, backend dielectric 120 is designated as “TEOS 120” in FIG. 1.
Backend dielectric TEOS 120 is covered with backend dielectric 130. In this example backend dielectric 130 is made of silicon oxynitride (SiON). Therefore, backend dielectric 130 is designated “SiON 130” in FIG. 1. Lastly, backend dielectric 130 is covered with backend dielectric 140. In this example backend dielectric 140 is made of plasma enhanced chemical vapor deposition (PECVD) oxide. Therefore, backend dielectric 140 is designated “PECVC oxide 140” in FIG. 1.
The fabrication process for a single poly NVM device is compatible with CMOS devices. The polysilicon gate in an NVM device is a floating gate (FG) that store electrons. The backend dielectric layers (TEOS 120, SiON 130, PECVD oxide 140) have a higher density of defects/traps than a front end gate oxide layer. The higher density of defects/traps enhances the Trap-Assisted-Tunneling (TAT) of electrons in the oxide layers. The higher density of defects/traps enhances thermal excitation in the silicon oxynitride (SiON) layer.
In a CMOS process the silicon oxynitride (SiON) layer is designed to be leaky (i.e., to have more defects/traps) in order to prevent plasma induced damage. Electrons stored on the polysilicon floating gate 110 may tunnel through the TEOS layer 120 to arrive at the leaky silicon oxynitride layer 130 (SiON 130). From the SiON layer 130 the electrons can easily move to the substrate layer (not shown in FIG. 1). This results in a higher charge decay rate for electrons that are stored on the floating gate. This also results in retention degradation especially at higher temperatures.
FIG. 2 illustrates an energy band diagram 200 for the electron charge decay mechanism (i.e., backend charge leakage). The electrons (designated e− in FIG. 2) are initially located on the polysilicon floating gate (FG) 110. The electrons can leak out of the floating gate (FG) 110 through the TEOS dielectric layer 120 through Trap-Assisted-Tunneling (TAT). This is shown in FIG. 2 by an electron entering one of the traps in the TEOS layer 120. The electrons then pass into the silicon oxynitride (SiON) layer 130. As shown in FIG. 1 and in FIG. 2 the electrons move through the silicon oxynitride (SiON) layer 130 to the substrate (not shown in FIG. 1).
This backend charge leakage is a serious problem for CMOS compatible NVM devices. Several different methods have been explored to reduce the leakage of charge from the backend dielectric layers in order to improve CMOS compatible retention performance.
A first approach has been to add a mask to the silicon oxynitride (SiON) layer 130 to etch the silicon oxynitride (SiON) layer 130 away from the top of the floating gate (FG) 110. The mask allows the SiON layer 130 to be selectively etched from the top of the NVM devices. The SiON layer 130 is left on top of the CMOS devices. The absence of SiON layer 130 over the top of the floating gate (FG) 110 breaks the charge leakage path. Electrons on the floating gate (FG) 110 therefore have a much slower decay rate by tunneling in oxide instead of going through a relatively leaky SiON layer 130 that is connected to the substrate.
A second approach has been to increase the thickness of the TEOS layer 120. This increases the tunneling distance from the floating gate (FG) 110 to the SiON layer 130. This causes the electrons to take a longer time to arrive at the relatively leaky SiON layer 130.
A third approach has been to modulate the density of the defects/traps in the SiON layer 120 in order to make the SiON layer 120 highly non-conductive. The fewer defects/traps there are in the SiON layer 120, the less conductivity there is in the SiON layer 120. Electrons that arrive at the SiON layer 120 will have difficulty in traveling to other locations. The electrons that collect in the SiON layer 120 will deter further leakage of electrons from the floating gate (FG) 110.
CMOS compatible NVM performance is not as good as other mainstream NVM technology (e.g., stacked gate NVM, split gate NVM, SONOS (silicon-oxide-nitride-oxide-silicon) NVM). CMOS compatible NVM performance has slow speed, low density and limited endurance. But it has one major advantage. It has low cost because its fabrication process is compatible with CMOS processes. CMOS compatible NVM technology is advantageous in some applications where limited speed, density and endurance NVM technology is needed but the cost would be too high if mainstream NVM technology were employed. Therefore, the low cost feature is critical to CMOS compatible NVM technology.
The three approaches mentioned above for improving CMOS compatible NVM retention performance have significant drawbacks. The first approach requires the addition of a mask and etch step to the standard CMOS process. This increases the cost. More importantly, when etching the SiON layer 130 from the top of the floating gate (FG) 110, limited etch selectivity between the SiON layer 130 and the TEOS layer 120 always leads to some over-etch of the TEOS layer 120. A thinner TEOS layer 120 will lead to an increased level of electron discharge from the floating gate (FG) 110. In addition, etching away the SiON layer 130 will expose the floating gate (FG) 110 and the TEOS layer 120 to backend plasma damage. This will lead to a degradation of the NVM device retention.
The second approach requires an increase in the thickness of the TEOS layer 120. In order to get a satisfactory retention performance the TEOS layer 120 needs to have at least a double thickness. The creation of a thicker TEOS layer 120 alters the CMOS process and significantly alters the device parameters. After this step the NVM device is no longer CMOS compatible.
The third approach results in plasma induced damage. The CMOS process requires that the SiON layer 130 be leaky so that charges from the plasma process have a leakage path.
Therefore, there is a need in the art for a system and a method that can (1) reduce charge leakage from the floating gate, and (2) not result in plasma induced damage, and (3) not significantly change CMOS device parameters. There is a need in the art for a system and a method that can balance the NVM retention requirements and the CMOS device requirements. There is a need in the art for a system and a method that can fabricate NVM devices and CMOS devices in the same manufacturing process.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document; the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.